A computer system can include a number of separate resources, such as processors, memories, and I/O devices, in order to perform various tasks. During operation of the computer system, it is often necessary for commands and/or data to be transferred between different resources in the computer system. Typically, a system bus is provided for transferring messages between a number of resources, or nodes, in a multiple node network.
In order to effectively utilize a common system bus for transfer of messages between resources, access to the bus by each of the resources must be carefully controlled. In particular, only one resource can attempt to transfer messages onto the system bus at any one time. For example, one resource may be ready to send out a read command during a particular bus cycle, while at the same time another resource is ready to obtain access to the bus for several bus cycles in order to transmit a write command and write data.
Therefore, in every computer system including a number of nodes coupled to a common bus, some form of "arbitration" must be performed in order to determine which node obtains access to the bus. A central arbiter can be coupled to each of the bus system resources and can determine which resource will be granted access to the bus during any given bus cycle. Such a central arbiter receives separate bus requests from each of the resources at times when that resource is ready to obtain access to the bus in order to transmit a message to another resource. In response to a number of bus requests, the central arbiter sends a bus grant to only one of the requesting nodes in a predetermined manner corresponding to a priority assigned to each request.
The use of bus request signals results in more efficient utilization of the bus and the system resources. Bus access is granted to a node only when that resource is performing an operation that requires transmission of a message by that resource onto the bus.
Unfortunately, certain types of transfers from a resource to the bus cannot be completed within a single bus cycle. For example, write transfers require that the resource be given access to the bus for more than one bus cycle. The message transferred onto the bus during the first bus cycle (command cycle) of the write transfer will be a write command. During the next consecutive bus cycle, write data will be transferred onto the bus.
To accomodate such multicycle transfers, an arbitration method may be used in which a resource performing a multicycle transfer operation must transmit an activated extend bus cycle signal to the central arbiter. The central arbiter would then determine whether it has received an activated extend bus cycle signal before generating a bus grant for a selected node. In these systems, issuance of the bus grant is delayed while the central arbiter processes the activated extend bus cycle signal. If an extend bus cycle signal is activated, the central arbiter transmits the bus grant to the same resource that had access to the bus during the preceding bus cycle.
An important disadvantage exists in systems utilizing such an arbitration method. Resources in the computer system obtain access to the bus based solely on the presence of a bus grant from the central arbiter. Therefore, the performance of the system and the effective utilization of the common bus depends upon the speed with which the bus grant is transmitted to a selected resource. This arbitration method, however, requires a relatively long bus cycle time because the arbiter must wait for the receipt of the extend bus cycle signal before generating a new grant. For systems that use a single wired-OR extend bus cycle signal, this would delay the availability of the grant.
It would be undesirable, however, to solve this problem by adding additional extend bus cycle lines from the resources to the central arbiter to increase the speed at which the arbiter can determine if the previous owner of the bus should retain ownership for the next cycle. Such a solution would require the addition of several pins on the backplane to supply another interconnect from each resource to the arbiter, and such pins may not be available.
It is an object of the present invention to reduce system bus cycle time by reducing the arbitration time, thereby improving system performance.
Another object of the present invention is to provide this reduced arbitration time with only one extend bus cycle line on the back plane.
It is a further object of the invention to arbitrate between bus requests from several resources, and to have the central arbiter conditionally indicate which resource has been selected, without delaying the selection by the arbiter in order to process additional signals from resources contending for access to the bus.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.